Memory devices, such as dynamic random access memories (DRAMs), enjoy wide use in electronic devices. DRAMs can be considered “dynamic” in that memory values can be lost unless continually (i.e., dynamically) refreshed. Conventional DRAMs can have a very high capacity to store data, as compared to other memory device types, and are relatively less costly when compared to other memory device types. Conventional DRAMs can typically include a number of banks each of which includes multiple rows of memory cells. A bank selection operation can be used to select which bank can be active at a given time.
In a conventional DRAM, a row can be accessed by first “activating” a row within a given bank. Such an activation typically includes the application of a certain combination of control signals along with a row address. Even more particularly, in a synchronous DRAM, a row can be activated by different combinations of a chip select (CS) signal, row address strobe (RAS) signal, column address strobe (CAS) signal, and write enable (WE) signal. Different combinations can indicate different command types, including, but not limited to, ACTIVE, READ, WRITE, and PRECHARGE commands. Accesses typically start by activating a row with an ACTIVE command.
Following a row access, a precharge command can be issued to precharge bit lines and thus condition the bank for a subsequent access. Such a feature can give rise to an active-to-active timing parameter (TRC). A parameter TRC can refer to a minimum allowable time between two row activation cycles on a same bank.
To better understand various features of the disclosed embodiments, a conventional memory device will now be described.
A block diagram of a conventional DRAM with a multi-bank architecture is shown in FIG. 7, and designated by the general reference character 700. A DRAM 700 can include a core 702 (where data is stored) arranged in the form of a number of memory array banks, typically either effectively 4 or 8 in number.
Accesses to a DRAM can involve opening a row in a particular bank (row activation) and then selecting a particular column, along with the assertion of the appropriate control signals. Following row activation, the same row can then be “closed” (or precharged), before a different row of the same bank can be accessed. The above sequence can take several cycles (e.g., minimum of 8) and hence can limit the frequency at which a bank can be accessed. In other words, a first activation of a row can make the bank ‘unavailable’ (for a subsequent access to a different row) for a specific period of time. This time period of TRC can be a critical specification in a DRAM device. In particular, if a second successive access to the same bank happens such that it violates the TRC limit, the access can be unsuccessful.
Referring now to FIG. 8, a timing diagram shows one example of a conventional TRC timing arrangement. FIG. 8 shows a read operation for an address multiplexed synchronous DRAM. FIG. 8 shows a clock signal CLK, an applied address “Address”, an applied command “Command”, a data output “Data”. At time t0, a row in a particular bank can be activated by application of an activate command ACT along with a row address ROW. At time t1, a read command RD can be issued along with a column address COL. At time t2, a burst of read data can start to be output beginning with data value DQ1.
At time t3, a predetermined time before a last data value DQ4 is output, a precharge command PRE can be issued. At this time, bit lines have already output data value DQ4 (or currently outputting such data). Thus, a precharge operation can be initiated. However, while such a precharge operation is taking place, the same bank may not be accessed. As a result, there is a “bank lockout period” 800 between times t3 and t4, during which a new active command may not be received, or be considered invalid.
At time t4, precharge operations are completed, and a new active command can be issued.
Thus, in FIG. 8, a parameter TRC extends from time t0 to t4.
Conventional SDRAMS with a banked architecture can enable the pipelining of accesses to the memory. In particular, multiple banks can be active at the same time, thereby allowing for faster access. However, as explained above, in accessing a row, the bank must be conditioned with an activate command and subsequently closed with a precharge command.
A drawback to conventional arrangements can be that an SDRAM controller, different from the SDRAM devices, typically must track bank availability. An SDRAM controller is typically a different integrated circuit device that issues commands and addresses to one or more SDRAMs. As a result, SDRAM controllers can be increasingly more complex, having to track multiple operations and states of corresponding SDRAMs, including bank availability. Failure to keep track of bank availability can result in access failures. While conventional solutions have an SDRAM controller tracking bank availability, this can limit an SDRAM controller as other operations that can be started during a bank lockout period may be overlooked.